What is the difference between dynamic power and leakage (static) power?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Dynamic power flows only when nodes switch: every 0-to-1 transition charges a capacitance from the supply. Leakage power flows all the time the transistors are powered, even with the clock stopped, because off transistors are never fully off. You cut dynamic power by switching less or at lower voltage, and leakage by using higher-Vt cells or removing the supply.
Technical Explanation
- Dynamic power: current drawn to charge and discharge load capacitance, plus brief short-circuit current, each time a signal toggles.
- It scales with activity, capacitance, frequency and the square of voltage, so a stopped clock drops it almost to zero.
- Leakage power: current through transistors that are nominally off, present whenever the supply is up.
- Leakage depends on threshold voltage, temperature and process corner, not on activity, so an idle block still leaks.
- Dynamic reducers: clock gating, operand isolation, lower voltage, lower frequency. Leakage reducers: HVT cells, body bias, power gating.
- At advanced nodes leakage can be a large share of total power at hot corners, so idle time decides which reducer pays off.
- Clock gating alone saves nothing on a block that sits idle for seconds; only cutting its supply removes leakage.
Formula Or Decision Rule
- Total: P_total = P_dynamic + P_leakage
- Dynamic: P_dynamic ā Ī± Ā· C Ā· VĀ² Ā· f (Ī± = activity factor, C = switched capacitance)
- Leakage: P_leakage = V Ā· I_leak, with I_leak set by Vt, temperature and corner, not by Ī± or f
Common Mistake
The Trap: Assuming a clock-gated block consumes no power.
- Its leakage keeps flowing as long as the supply is on, and at hot corners that leakage can exceed the dynamic power you saved.
- Long-idle blocks need power gating, not just clock gating.
Follow-up Question & Model Response
"Which one dominates in a modern mobile SoC?"
Candidate Model Response: It depends on the mode. When the chip is busy, dynamic power usually dominates the active blocks. When the phone sits in standby, clocks are gated and leakage becomes most of what drains the battery. That is why mobile chips combine clock gating for active modes with power gating for standby.
Practical Example
Design Scenario: (illustrative) Block PD_DSP has Ī± = 0.1, C = 2 nF, V = 0.9 V, f = 500 MHz: P_dynamic ā 0.1 Ć 2 nF Ć 0.81 Ć 500 MHz ā 81 mW. Its leakage is I_leak = 20 mA at 0.9 V, so 18 mW. Gate the clock and 81 mW goes to near zero, but the 18 mW stays until PD_DSP is powered down. Over 10 hours of standby that is 180 mWh, a noticeable slice of a phone battery.
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