Why does reducing supply voltage (Vdd) help reduce power, and what is the trade-off?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Dynamic power scales with the square of supply voltage, so a small voltage cut gives a large power saving, and leakage drops too. The price is speed: gate delay rises as Vdd gets closer to the threshold voltage. Below a floor set by Vt and memory stability, the logic slows badly or stops working reliably.
Technical Explanation
- V² effect: switching energy per transition is C · V², so going from 1.0 V to 0.9 V cuts it by about 19%.
- Leakage also falls with lower Vdd, partly through reduced drain-induced barrier lowering, so both components improve.
- Delay penalty: drive current depends on (Vdd - Vt), so delay rises steeply as Vdd approaches Vt.
- Lower voltage means lower frequency, so energy per task improves most when the work can tolerate running slower.
- Voltage floor: SRAM bit cells and timing margins set a minimum Vdd; below it reads fail or noise margins vanish.
- This is why chips use multiple voltages, DVS and DVFS: full voltage only where and when speed is needed.
Formula Or Decision Rule
- Dynamic: P_dyn ≈ α · C · V² · f, so P scales with V² at fixed f
- Delay (alpha-power model): t_d ∝ V / (V - Vt)^a, with a between 1 and 2
- Rule: lower V until timing slack or the Vmin floor runs out, whichever comes first
Common Mistake
The Trap: Lowering Vdd on a block without re-running timing at the new voltage.
- Setup fails at the slow corner, and any crossing into a higher-voltage domain now needs level shifters that were never inserted.
- Re-run STA at the new voltage and re-check the direction of every crossing before you sign off the change.
Follow-up Question & Model Response
"If voltage and frequency both drop, how much does power fall?"
Candidate Model Response: Dynamic power scales with V² · f, so it falls roughly with the cube of the scaling factor. Dropping both V and f by 10% leaves about 0.9³ ≈ 73% of the original power. Energy per operation falls only with V², because the task now takes longer. That still saves battery, which is the reason DVFS exists.
Practical Example
Design Scenario: (illustrative) PD_DSP runs at 1.1 V and 800 MHz, drawing 200 mW dynamic. Moving to 0.9 V gives (0.9/1.1)² ≈ 0.67, so about 134 mW at the same clock, but the slow corner now meets only 600 MHz. Run at 600 MHz and power drops to about 100 mW, since 0.67 × 0.75 ≈ 0.50 halves the original 200 mW. Signals from PD_DSP into the 1.0 V PD_MYCHIP now cross low-to-high and need level shifters.
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