Level 4: Signoff Reasoning

Expert MMMC Interview Questions

Reason through ECO side effects, correlation gaps, parasitic coverage, PBA/GBA, SI, and signoff acceptance.

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What to practise at this level

Treat every result as scoped evidence. Compare environments, validate coverage, and cross-check every physical change across all required views.

  1. 01 A setup ECO improves WNS by 100 ps in one view but creates hold violations in two other views. What actually happened?Expert: A setup ECO fixes slow-corner timing by upsizing cells or swapping to lower threshold-voltage (LVT/ULVT) cells. Because that physical silicon change applies across all views, it accelerates data arrival in the fast hold corners (FF/-40°C), creating new hold violations.
  2. 02 Why might ICC2 report clean timing while PrimeTime signoff on the same design shows failures?Expert: ICC2 uses streamlined delay calculation approximations and simplified modeling to maintain fast PnR optimization turnaround. PrimeTime is the golden signoff timer that uses exhaustive CCS/ECSM current-source models, full PrimeTime-SI crosstalk analysis, and path-based analysis (PBA).
  3. 03 Timing changed dramatically between two runs, but the netlist is provably identical. What do you compare first?Expert: When identical netlists yield different timing results, first compare the environment and input files: diff the SDC constraints, check SPEF annotation coverage and corner settings (`report_annotated_parasitics`), verify library release versions, and audit tool variables and OCV derates (`report_ocvm`).
  4. 04 SPEF loaded without a fatal error, but one critical net reports almost zero net delay. Does that prove parasitic annotation is correct?Expert: No. A clean `read_spef` command only confirms syntax validity. If net or instance names in the SPEF do not match the gate netlist (e.g. hierarchy delimiter mismatches or renamed ECO nets), the tool silently ignores the parasitics and defaults to zero wire delay.
  5. 05 Why can a change in RC alone also change cell delay, even when the cell itself is untouched?Expert: Cell delay depends on output capacitive load ($C_{load}$) and input transition time (slew). A higher RC corner increases the capacitive load on the cell's output (slowing it down) and degrades interconnect slew, delivering a slower transition to all downstream receiver cells.
  6. 06 Why might the globally worst-WNS scenario not be enough, by itself, to decide which views can be removed from a signoff plan?Expert: Different analysis views have different critical paths. The worst-WNS scenario may constrain the high-speed functional datapath, while another scenario with lower WNS may be the only view that exercises scan test chains, asynchronous interfaces, or low-power retention paths.
  7. 07 Graph-based analysis (GBA) and path-based analysis (PBA) give significantly different slack on the same critical path. What's going on, and which one do you trust?Expert: GBA (Graph-Based Analysis) is conservative and pessimistic: at multi-input gates, it assumes worst-case input slew across all inputs propagates to the output, compounding pessimism down the tree. PBA (Path-Based Analysis) re-evaluates the path using the exact propagating slew. PBA is trusted for signoff because it removes artificial mathematical pessimism.
  8. 08 Why can enabling signal integrity (SI) analysis change which corner or view is actually the worst one?Expert: Enabling Signal Integrity (SI) analysis introduces crosstalk delta delays ($Delta t$) caused by switching aggressor nets. Corners with fast switching slews (FF) or lower supply voltages can experience severe crosstalk slowdown or speedup that changes which corner exhibits the worst slack.
  9. 09 A view is named FUNC_SS_RCMAX, but its actual configured objects point to an FF library and a different RC condition. What does the timing engine use?Expert: The timing engine uses the actual bound physical objects (the linked `library_set` and `rc_corner`), completely ignoring the string name of the view. A view named `FUNC_SS_RCMAX` that points to an FF library will evaluate fast-process physics, silently producing invalid setup results.
  10. 10 An engineer tells you "timing is clean." As the signoff lead, what do you ask before accepting that statement?Expert: As signoff lead, ask for the complete signoff audit evidence: (1) Was the full signoff matrix active (all modes × all corners)? (2) Is `check_timing` clean with zero unconstrained endpoints? (3) Is parasitic annotation 100% verified via `report_annotated_parasitics`? (4) Was PrimeTime SI crosstalk enabled? (5) Were PBA reports run on near-critical paths? (6) Are min-pulse-width and max-transition design rules clean?

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