What is the difference between recovery/removal checks and setup/hold checks?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Recovery and removal are the asynchronous-control equivalents of setup and hold, but applied to a register's set or clear pin rather than its data pin. Recovery is setup-like โ the control signal must be de-asserted early enough before the clock edge. Removal is hold-like โ the signal must stay asserted long enough after the edge before releasing.
Technical Explanation
- What pin they police. Setup and hold constrain the data pin of a register. Recovery and removal constrain a different pin entirely: the asynchronous set or clear (commonly called preset or reset) that can force a register's state independent of the clock.
- Recovery is the setup analogue. A recovery check verifies that the asynchronous control signal โ typically a reset โ is de-asserted (released) early enough before the next active clock edge for the register to reliably resume normal, clocked operation on that edge. Like setup, it is about giving the circuit enough margin before the edge.
- Removal is the hold analogue. A removal check verifies the opposite side of the same edge: the asynchronous control must stay asserted long enough after the clock edge โ or, equivalently, must not be released too soon after it โ so the edge does not catch the register mid-transition out of reset. Like hold, it is about stability after the edge.
- Why this distinction exists at all. An asynchronous reset is, by definition, not gated by the clock โ it can change state at any moment. But the moment it releases still has to be properly timed relative to the clock, or the register can land in an unpredictable, indeterminate state instead of cleanly resuming operation. Recovery and removal checks are exactly how STA verifies that release moment.
- What breaks if this is skipped. A design with no recovery/removal checking might look completely clean in a report that only checks data setup/hold, because those checks never touch the reset pin at all โ the reset-release hazard would only ever surface as an intermittent, hard-to-reproduce failure after silicon.
Common Mistake
The Trap: Assuming an asynchronous reset pin is entirely outside STA's scope simply because it is not clocked.
- "Asynchronous" only describes how the signal can assert, not whether its release is timing-sensitive.
- Overlooking this leaves the reset-release moment completely unverified, and the resulting failure โ a register waking up in a random state on power-up or after a reset pulse โ tends to look like a functional bug rather than a timing one, making it much harder to trace back to its real cause.
Follow-up Question & Model Response
If a design uses a reset synchronizer to release reset synchronously to the clock, are recovery and removal checks still needed?
Candidate Model Response: Yes, though the risk is reduced rather than eliminated. A reset synchronizer aligns the release edge to the clock, which is why teams use them โ to make recovery/removal timing predictable instead of arbitrary. But the synchronizer's output still drives real reset pins on downstream flops, and that final leg of the reset tree still has routing delay the checks need to verify, especially if the reset fans out to flops at very different distances. Skipping the checks ignores that the synchronizer only fixes the source of the release edge, not the delay to every flop it reaches.
Practical Example
A block has an asynchronous active-low reset (RST_N) clocked at 300 MHz (3.33 ns period). A reset synchronizer releases RST_N aligned to a rising edge, but the reset net fans out through several buffers to the farthest flop, adding 0.4 ns of routing delay. A recovery check on a flop closer to the synchronizer, where the release edge and the next active clock edge are only 0.5 ns apart, shows just 0.08 ns of recovery slack โ a path a data-only setup/hold report would never surface.
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