Setup vs Hold Time, Slack, Skew, and Jitter: Complete STA Interview Guide
Static Timing Analysis (STA) interviews test fundamental silicon timing behavior: how sequential registers reliably capture and hold digital state across process, voltage, temperature variations, and clock distribution networks. This comprehensive guide covers core mathematical derivations, physical mechanisms, PrimeTime report analysis, and high-frequency interview traps.
1. Direct Answer & Key Definitions
Setup time (Tsetup) is the minimum duration before the active capture clock edge during which sequential input data must remain stable. Hold time (Thold) is the minimum duration after the active capture clock edge during which data must remain stable. A setup violation causes late data arrival and metastability on the current cycle; a hold violation causes premature data overwrite, corrupting the capture flip-flop. Setup checks are max-delay constraints dependent on clock frequency; hold checks are min-delay zero-cycle constraints completely independent of clock frequency.
In digital synchronous ASIC design, timing closure guarantees that millions of flip-flops can operate concurrently without entering metastable states or sampling corrupted data. Static Timing Analysis (STA) verifies these timing constraints exhaustively across all register-to-register, input-to-register, register-to-output, and feedthrough paths under worst-case Process, Voltage, and Temperature (PVT) corners without requiring dynamic simulation test vectors.
2. Setup Check Anatomy & Equations
A setup check ensures that the combinational logic signal launched by a source flip-flop settles to a valid, stable logic level before the destination capture flip-flop samples the data input pin (D). If data arrives too late, the internal bistable latch inside the flip-flop fails to resolve within the setup aperture, causing the output Q to oscillate or hover at an intermediate voltage level (metastability).
Because setup verification is a multi-cycle transition (typically one full clock period in single-cycle paths), the total allowable budget includes the clock period Tclk:
T_launch + T_clk2q_max + T_comb_max ≤ T_capture + T_period - T_setup - T_uncertainty_setup + CRPR
Setup Slack = (T_capture + T_period - T_uncertainty_setup - T_setup + CRPR) - (T_launch + T_clk2q_max + T_comb_max)
Where the key timing parameters represent:
T_launch: Clock network propagation delay from the root clock source to the clock pin (CK) of the launch flip-flop under late corner conditions.T_clk2q_max: Maximum clock-to-Q internal cell propagation delay of the launching register.T_comb_max: Maximum cumulative delay through combinational logic gates and routing wire interconnects (late derates, highest temperature, lowest voltage).T_capture: Clock network propagation delay to the capture register under early corner conditions.T_period: The operational clock cycle time (1 / fclk).T_setup: Standard cell library setup time requirement of the capture register.T_uncertainty_setup: SDC margin accounting for clock jitter, PLL phase error, and signoff guardband.CRPR: Clock Reconvergence Pessimism Removal credit for common clock path buffers.
3. Hold Check Mechanics & Min-Delay Rules
A hold check guarantees that new data launched by the active clock edge does not propagate through fast combinational logic so quickly that it overwrites the previous data value before the capture register has finished sampling it. Unlike setup, hold verification is a same-edge (or zero-cycle) comparison where the launch and capture clock events originate from the same active clock transition.
Because the launch and capture edges are identical in time at the clock root, the clock period Tperiod does not appear in the hold timing check:
T_launch + T_clk2q_min + T_comb_min ≥ T_capture + T_hold + T_uncertainty_hold - CRPR
Hold Slack = (T_launch + T_clk2q_min + T_comb_min + CRPR) - (T_capture + T_hold + T_uncertainty_hold)
A chip with setup timing violations can often be tested and operated in the lab by lowering the clock frequency (increasing Tperiod). A chip with an uncorrected hold violation is permanently defective silicon (dead on arrival) because slowing the clock does not add a single picosecond of hold margin.
4. Setup vs Hold Detailed Comparison
Understanding the exact trade-offs between setup and hold verification is fundamental for STA and physical design interviews:
| Parameter / Attribute | Setup (Max-Delay Check) | Hold (Min-Delay Check) |
|---|---|---|
| Constraint Type | Maximum delay path constraint | Minimum delay path constraint |
| Clock Relationship | Next-cycle check (Edge 0 to Edge 1) | Same-cycle check (Edge 0 to Edge 0) |
| Clock Period (Tclk) | Directly determines slack (+Tclk) | Independent of Tclk (not in equation) |
| Operating Corner (Data) | Slow-Slow (SS), low voltage, high/low temp | Fast-Fast (FF), high voltage, low/high temp |
| Positive Clock Skew | Beneficial (adds timing budget) | Detrimental (steals hold margin) |
| Negative Clock Skew | Detrimental (steals setup budget) | Beneficial (improves hold margin) |
| Crosstalk Impact | Aggressors switching in opposite direction (slowdown) | Aggressors switching in same direction (speedup) |
| Lab Mitigation | Reduce clock frequency (fclk ↓) | None — chip cannot function correctly |
| Physical Fixing Strategy | Upsize gates, LVT swap, useful skew, buffer removal | Insert delay buffers, HVT swap, downsize drivers |
5. Slack Calculation & Signoff Margins
Slack represents the timing margin by which a design meets or violates its performance targets. In PrimeTime and Tempus signoff, positive slack represents timing closure compliance; negative slack (a timing violation) must be closed prior to tapeout:
- Worst Negative Slack (WNS): The largest negative slack value across all analyzed paths in a clock domain or scenario. WNS determines the maximum operating frequency penalty.
- Total Negative Slack (TNS): The arithmetic sum of all negative slacks across all violating endpoints. TNS measures overall design closure difficulty and optimization progress.
- Failing Endpoints (NVP): The count of unique register or output pins exhibiting negative slack.
6. Positive vs Negative Clock Skew
Clock skew is the spatial variation in arrival times of an active clock edge across two distinct sequential elements on the chip: T_skew = T_capture_clock - T_launch_clock.
- Positive Clock Skew (Tcapture > Tlaunch): The clock edge reaches the capture register later than the launch register. This extends the available combinational logic window for setup checks (+Tskew added to setup budget). However, it directly degrades hold margin because new data starts propagating while the capture clock is delayed.
- Negative Clock Skew (Tcapture < Tlaunch): The clock edge reaches the capture register earlier than the launch register. This reduces the available setup budget, making timing closure harder, but naturally provides extra hold margin.
- Useful Skew (Concurrent Clock & Data / CCD): In modern physical synthesis (ICC2 / Innovus), timing engines deliberately adjust clock tree buffer delays to introduce controlled positive skew on timing-critical paths, borrowing slack from adjacent paths that have surplus positive margin.
7. Clock Jitter & SDC Uncertainty Modeling
While clock skew represents spatial variation across physical locations, clock jitter represents temporal variation in clock edge arrival over successive clock cycles at the same physical node. Jitter is caused by PLL phase noise, thermal variations, and power supply ripple.
In SDC constraints, designers use set_clock_uncertainty to model jitter, duty cycle distortion, and signoff margin:
# Setup uncertainty includes clock jitter, PLL phase error, and signoff guardband
set_clock_uncertainty -setup 0.120 [get_clocks SYS_CLK]
# Hold uncertainty models clock skew jitter and duty cycle distortion
set_clock_uncertainty -hold 0.040 [get_clocks SYS_CLK]
Notice that setup uncertainty is typically significantly larger than hold uncertainty. Setup uncertainty must absorb cycle-to-cycle period jitter across two successive clock edges, whereas hold uncertainty only models edge-to-edge variation across the same clock transition.
Practice Full Q&A: Clock uncertainty vs clock jitter distinction8. Real PrimeTime Report Walkthrough
Below is a realistic Synopsys PrimeTime setup timing report showing how data arrival time and data required time are calculated line-by-line:
--------------------------------------------------------------------------
clock SYS_CLK (rise edge) 0.00 0.00
clock source latency 0.20 0.20
u_clk_buf_1/Y (CLKBUF_X8) 0.12 0.32 r
u_launch_reg/CLK (DFF_X1) 0.08 0.40 r (launch clock)
u_launch_reg/Q (DFF_X1) 0.15 0.55 f (clk-to-Q)
u_alu_add/U12/Y (NAND2_X2) 0.09 0.64 r
u_alu_add/U45/Y (AOI22_X2) 0.18 0.82 f
u_capture_reg/D (DFF_X2) 0.11 0.93 r (data arrival time)
--------------------------------------------------------------------------
clock SYS_CLK (rise edge) 1.00 1.00 (clock period)
clock source latency 0.20 1.20
u_clk_buf_1/Y (CLKBUF_X8) 0.11 1.31 r
u_capture_reg/CLK (DFF_X2) 0.07 1.38 r (capture clock)
clock reconvergence pessimism removal 0.02 1.40
clock uncertainty -0.10 1.30
library setup time -0.08 1.22
data required time 1.22
--------------------------------------------------------------------------
data required time 1.22
data arrival time -0.93
--------------------------------------------------------------------------
slack (MET) 0.29
9. Fixing Setup vs Hold in Implementation
During physical synthesis, CTS, routing, and post-route ECO loops, timing engineers apply distinct strategies to close setup and hold violations without creating secondary timing regressions:
- Fixing Setup Violations: Upsize driving standard cells, swap high-Vt (HVT) cells to low-Vt (LVT/ULVT), restructure logic hierarchies, insert pipeline registers, reduce wire parasitics via wider metal layers, or apply useful skew.
- Fixing Hold Violations: Insert delay buffers (or lockup latches across clock domains) on fast data paths, downsize driving gates, swap ULVT/LVT cells to SVT/HVT cells to increase cell propagation delay without increasing area or power excessively.
10. Three High-Yield Interview Traps
Many candidates say: "If hold fails, we can run the chip slower in post-silicon bring-up." This is completely wrong. Hold checks are zero-cycle checks; Tperiod does not exist in the hold slack formula. A hold violation means old data was destroyed before it could be latched, causing unrecoverable data corruption at any clock speed.
Positive clock skew gives more time to the launch-to-capture path for setup, but it takes away the exact same amount of margin from the hold check. Uncontrolled positive skew causes severe hold violations that require adding hold buffers, which increases dynamic power and routing congestion.
Candidates often confuse spatial skew (caused by physical wire length and buffer differences) with temporal jitter (caused by PLL noise and power supply fluctuations). In modern SDC, skew is explicitly propagated after CTS via set_propagated_clock, while uncertainty models jitter and margin.
11. High-Frequency Interview FAQs
What is the fundamental difference between a setup check and a hold check?
A setup check is a max-delay constraint ensuring data arrives before the next active capture clock edge by at least Tsetup. A hold check is a min-delay constraint ensuring newly launched data does not overwrite currently sampled data before Thold.
Why can hold violations not be fixed by reducing clock frequency?
Hold checks occur between the same clock edge (or edge 0 to edge 0). The clock period (Tclk) does not appear in the hold slack equation: Slack_hold = Arrival_min - (T_capture + Thold). Changing clock frequency has zero impact on hold margin.
How does positive clock skew affect setup and hold margins?
Positive skew (capture clock arrives later than launch clock) helps setup margin by providing more time for data propagation, but harms hold margin because data must remain stable longer.
What is the difference between clock jitter and clock skew?
Clock skew is the spatial variation in arrival time between two distinct physical registers on the chip. Clock jitter is the temporal variation in clock period or edge placement over time at the same node.