What is the difference between pre-layout and post-layout STA?
From PDVerse STA Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Pre-layout STA runs on the synthesized netlist with ideal clocks and estimated wire delay, before physical placement exists. Post-layout STA runs on the actual routed design with propagated clocks and real extracted wire parasitics, and is the version that counts for signoff.
Technical Explanation
The same design gets timed twice, at two very different stages, and the numbers can look quite different because so much physical detail simply does not exist yet at the first stage.
- Pre-layout โ what exists: a synthesized gate-level netlist with no physical coordinates yet, so the tool has no real wires to measure.
- Pre-layout โ how wire delay is handled: the tool estimates it from a wire-load model or a rough placement guess, not from anything extracted.
- Pre-layout โ clocks: treated as ideal or given a flat estimated latency, since no clock tree has been built yet.
- Post-layout โ what changed: the design now has real cell locations, real routed wires, and a real clock tree synthesized and buffered.
- Post-layout โ why it is the real answer: wire delay comes from extracted parasitics rather than an estimate, clocks are propagated through the real tree, and crosstalk between neighboring wires can be included โ this is the version that actually has to be clean before tapeout.
Common Mistake
The Trap: Assuming a comfortable pre-layout slack number will still hold once the design is routed.
- Routing congestion, real clock skew, and crosstalk coupling can all eat into slack in ways a pre-layout estimate cannot see.
- Hundreds of picoseconds of margin can disappear between the two stages on a path that looked completely safe before layout.
Follow-up Question & Model Response
If post-layout STA is the version that actually matters for signoff, why bother running pre-layout STA at all?
Candidate Model Response: Pre-layout STA is cheap to run and catches fundamental problems early โ a missing clock constraint, an unconstrained port, or a logic path that is structurally too deep to ever meet timing regardless of layout. Finding those issues before spending days on placement and routing saves real schedule time, since fixing a structural problem after layout usually means redoing the layout as well. I would treat pre-layout STA as a fast filter for constraint and logic-depth problems, not as a stand-in for the real, extracted signoff numbers post-layout provides.
Practical Example
A path shows 0.45 ns of setup slack pre-layout using an estimated wire-load model. After routing, the same path's extracted parasitics and propagated clock skew bring that down to -0.08 ns, a genuine violation the pre-layout estimate never saw, driven mostly by the wire ending up on a congested, resistive route the estimate could not predict.
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