How does process corner (fast/typical/slow) affect power?

Short Answer

A fast (FF) corner has lower thresholds and stronger transistors, so it has the worst leakage and runs fastest. A slow (SS) corner has the least leakage but the worst setup timing. So the corner that fails timing is rarely the corner that fails power, and you sign off each at its own worst case.

Technical Explanation

• Process corner: the spread of transistor strength from wafer to wafer, named by NMOS and PMOS speed: FF, TT, SS and skewed FS and SF.
• At FF, lower Vt and shorter effective channels raise leakage sharply, often several times TT (illustrative).
• Dynamic power changes less with process at fixed voltage, since α · C · V² · f is mostly set by design and voltage.
• At SS, gates are slow, so setup timing is worst; leakage is lowest there.
• Leakage signoff therefore uses FF with high voltage and temperature, while setup uses SS with low voltage.
• Voltage and temperature stack on top of process: FF at the highest voltage and 125 °C is the leakage worst case, not FF alone.
• Some chips use adaptive voltage scaling so FF parts run lower voltage, trimming the power spread between fast and slow silicon.

Follow-up Question & Model Response

"Why do FS and SF corners matter if FF and SS already bound things?"

Candidate Model Response: Skewed corners stress circuits that depend on the balance between NMOS and PMOS strength. Level shifters, sense amplifiers and some memory cells can fail or draw extra current when one device type is much stronger than the other. Hold and duty-cycle checks can also be worst at a skewed corner. For bulk power numbers, though, FF and SS usually bound the range.