What is AVS (Adaptive Voltage Scaling), and how does closed-loop feedback make it different from open-loop DVFS?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
AVS trims a domain's supply voltage in a closed loop, using on-die monitors that measure how fast this particular die is right now. DVFS picks a voltage from a fixed table built for the slowest die at the worst temperature, so it wastes margin on typical and fast silicon. AVS runs on top of DVFS: DVFS chooses the frequency, and AVS finds the lowest voltage that still meets it.
Technical Explanation
- Open-loop DVFS: each operating point is a table entry, for example 1.2 GHz at 0.90 V, signed off at the slow corner.
- Closed-loop AVS: a monitor such as a ring oscillator or critical-path replica reports speed; a controller nudges the regulator up or down.
- Monitors track process, temperature, aging and IR drop together, so the voltage follows the real die instead of a worst-case guess.
- Typical and fast dies can run tens of millivolts lower than the table, and dynamic power scales with V squared.
- The loop must never step voltage down faster than the monitor can react, and it keeps a guard band for droop.
- Signoff changes: you must close timing across the whole AVS voltage range, not at one table point per frequency.
- A monitor that does not correlate with the real critical paths lets AVS undervolt the chip into silent timing failures.
Common Mistake
The Trap: Placing the speed monitors wherever there is space and assuming they track the real critical paths.
- If the monitor sits in a cool corner or uses a different Vt mix, it reads faster than the logic it protects.
- AVS then lowers VDD below what the hot, slow paths need, and failures appear only on some parts in the field.
Follow-up Question & Model Response
"If AVS finds the minimum voltage on its own, why do you still need a DVFS table?"
Candidate Model Response: The table sets the frequency levels software can request and the safe starting voltage for each one. AVS only fine-tunes voltage inside a range around that point. On a frequency change you still follow the DVFS order: raise voltage before raising frequency, and lower frequency before lowering voltage. AVS then trims downward once the new frequency is stable. If the loop fails or the monitor reports an error, the controller falls back to the table voltage, which is always safe.
Practical Example
Design Scenario: (illustrative) PD_CPU runs at 1.2 GHz with a DVFS table voltage of 0.90 V, set for the slow corner at 125 C. On a typical die at 60 C, the ring-oscillator monitor still passes at 0.82 V, and the controller settles at 0.84 V after a 20 mV guard band. Dynamic power falls by about (0.84 / 0.90)² ≈ 0.87, a 13% saving. PrimeTime signoff covers PD_CPU from 0.80 V to 0.90 V at 1.2 GHz so every voltage the loop can choose is timed. A slow die at 125 C gets no reduction and stays at 0.90 V, which is exactly the case the DVFS table was built for. The monitor sits next to the worst CPU critical paths and uses the same Vt mix, so its reading tracks the logic it protects.
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