How does temperature affect leakage power?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
Leakage rises steeply with temperature, because heat lowers the threshold voltage and increases subthreshold and junction current. Illustratively, a block can leak several times more at 125 °C than at 25 °C. That creates a feedback loop: more leakage makes more heat, which makes more leakage.
Technical Explanation
- Subthreshold leakage grows roughly exponentially with temperature because Vt drops and thermal carrier energy rises.
- Junction leakage also rises with temperature, so both main paths get worse together.
- Thermal feedback: leakage heats the die, heat raises leakage; the loop is stable only if the package removes heat fast enough.
- Thermal runaway happens when it cannot, and temperature climbs until the chip throttles or fails.
- This is why leakage signoff uses the hottest junction temperature, often 105 °C or 125 °C depending on the product spec.
- Hot spots matter: a dense CPU cluster can sit well above the die average, so leakage there is higher than the average implies.
- Power tools read leakage from libraries characterised at fixed temperatures, so the temperature you pick for the corner sets the number directly.
Common Mistake
The Trap: Quoting a leakage number measured or simulated at 25 °C as the power budget.
- The real chip runs hot, its leakage is several times larger, and the thermal and battery budgets both miss.
- Check leakage at the spec's maximum junction temperature, and at the hot-spot temperature for dense blocks.
Follow-up Question & Model Response
"Does higher temperature always make circuits slower too?"
Candidate Model Response: Not at advanced nodes. With low supply voltage, the drop in Vt with heat can outweigh the drop in mobility, so gates get faster when hot. This is temperature inversion, and it means the slowest timing corner can be cold rather than hot. Leakage, though, is still worst when hot. So timing signoff must cover cold corners as well as hot ones, while leakage signoff stays at the hottest corner.
Practical Example
Design Scenario: (illustrative) PD_DSP leaks 15 mW at 25 °C and 90 mW at 125 °C. In a phone with passive cooling, the SoC reaches 95 °C during a game and PD_DSP leaks about 55 mW idle. Check it against an exponential curve: 15 mW to 90 mW is a 6x rise over 100 °C, so at 95 °C you expect 15 × 6^0.7 ≈ 52 mW, close to the 55 mW seen. Gating PD_DSP when unused removes that heat and lowers die temperature, which lowers leakage in the neighbouring always-on blocks too.
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