What is DVFS, and what is the safe sequencing rule when raising or lowering voltage and frequency together?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
DVFS (dynamic voltage and frequency scaling) changes a domain's supply voltage and clock frequency at run time to match the workload. The safe rule is: raise voltage before frequency when going up, and lower frequency before voltage when going down, so the logic is never clocked faster than its current voltage supports.
Technical Explanation
- Lower voltage makes gates slower, so each voltage has a maximum safe frequency.
- Dynamic power scales with VĀ²Ā·f, so dropping both together gives a large saving at light load.
- Going up: ramp V, wait for the regulator's power-good signal, then raise f.
- Going down: lower f first, then ramp V down.
- Get the order wrong and, during the transition, the domain runs a frequency its voltage cannot meet: setup violations and corrupted state.
- Changing the PLL can need a relock time, so many designs run the domain from a safe backup clock while the PLL settles.
- Signoff must time every voltage/frequency point, and level shifters are needed where DVFS domains talk to fixed ones.
# Conceptual (not a tool command)
if target_perf > current_perf:
set_regulator(V_new)
wait_power_good()
set_pll(f_new)
else:
set_pll(f_new)
set_regulator(V_new)Common Mistake
The Trap: Programming the PLL and the regulator at the same time, or in whatever order the driver code happens to use.
- The mismatch window is short but real, and a setup failure there corrupts state without any clear symptom.
- RTL simulation rarely catches it, because the regulator and PLL models usually switch instantly.
Follow-up Question & Model Response
"Why wait for power-good instead of a fixed delay?"
Candidate Model Response: The regulator's ramp time varies with load, temperature and the size of the step. A fixed delay is either too short on a slow ramp or wastes time on a fast one. Power-good tells the controller the rail has actually reached its target. Only then is the higher frequency safe.
Practical Example
Design Scenario: (illustrative) A CPU domain moves from 0.7 V/800 MHz to 0.9 V/1.6 GHz. The controller commands 0.9 V, waits for power-good, then switches the PLL to 1.6 GHz. Coming back down, it first drops to 800 MHz, then lowers the rail to 0.7 V. If the PLL had jumped to 1.6 GHz while the rail was still near 0.75 V, paths signed off only at 0.9 V would fail setup for the length of the ramp. The whole up-step costs the regulator ramp plus any PLL relock, often tens of microseconds (illustrative), which the OS governor has to budget for.
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