What is VTCMOS (Variable Threshold CMOS), and how does dynamically biasing the body reduce leakage?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
VTCMOS changes transistor threshold voltage at runtime by driving the wells from a body-bias generator instead of tying them to VDD and VSS. In standby it applies reverse body bias to raise Vt and cut subthreshold leakage, and in active mode it returns to zero or forward bias for full speed. The block keeps its state because the supply stays on; only the wells move.
Technical Explanation
- Body effect: Vt depends on source-to-body voltage; pushing the body away from the source raises Vt.
- Reverse body bias (RBB): NMOS p-well below VSS, PMOS n-well above VDD; Vt rises and subthreshold leakage drops exponentially.
- Forward body bias (FBB): the opposite direction lowers Vt to recover speed, limited by the body-source diode turning on.
- VTCMOS needs separate well taps, well bias rails and an on-chip charge pump or regulator for the bias voltages.
- Unlike power gating, state is retained and wake-up only waits for the wells to settle, typically microseconds for a large well.
- Body effect weakens at advanced bulk and FinFET nodes, so RBB saves less there; FD-SOI back-gate biasing is much stronger.
- Wrong bias polarity or an unconnected well tap forward-biases junctions and can raise leakage or cause latch-up.
Common Mistake
The Trap: Assuming reverse body bias always saves leakage, at any node and any bias level.
- Past a point, junction leakage and gate-induced drain leakage rise with RBB and cancel the subthreshold saving.
- At FinFET nodes the body effect is small, so a bias generator, its charge pump and the separate well-tap cells can cost more area and power than they save. Measure the leakage versus bias curve on your own node before committing to RBB.
Follow-up Question & Model Response
"How does VTCMOS differ from power gating when a block goes idle?"
Candidate Model Response: Power gating cuts the supply, so leakage drops to nearly zero but logic state is lost unless you add retention. VTCMOS keeps the supply on and only raises Vt, so leakage falls by a smaller factor but every flop keeps its value. Wake-up is faster because only the wells must settle, not a whole virtual rail. Designers pick VTCMOS for short idle periods and power gating for long ones. Some designs use both: bias during short gaps, full shutdown during long standby.
Practical Example
Design Scenario: (illustrative) PD_DSP idles for 5 ms between audio frames. Tying its p-well to -0.3 V and n-well to VDD + 0.3 V in standby raises NMOS and PMOS Vt enough to cut leakage from 8 mW to about 2 mW on this node. The bias generator itself draws 0.2 mW. Wells settle in about 10 µs, well inside the 5 ms idle window, and no retention cells are needed because the supply never drops. The cost shows up in physical design: PD_DSP needs its own well-tap cells tied to the bias rails instead of VDD and VSS, plus bias straps in the power grid. For idle gaps longer than about a second, the team would switch to power gating, where leakage falls close to zero.
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