What are the three components of dynamic power dissipation in a CMOS gate?

Short Answer

The three components are switching power, short-circuit power, and glitch power. Switching power charges the load capacitance on every useful transition, short-circuit power flows while both transistors conduct during a slow input edge, and glitch power comes from extra, unwanted transitions before a node settles. In libraries, the short-circuit part is usually modelled inside the cell as internal power.

Technical Explanation

• Switching power: each 0-to-1 output transition draws C_L · V² from the supply; half is stored, half burned in the PMOS.
• Short-circuit power: during an input edge both PMOS and NMOS are briefly on, so current flows straight from VDD to VSS.
• Short-circuit current grows with slow input slew, which is why max-transition limits also protect power.
• Glitch power: unequal path delays make a node toggle several times before it settles, and each toggle costs switching power.
• Liberty cells report internal power (short-circuit plus internal node charging) separately from the switching power of the output net.
• Switching power usually dominates; short-circuit and glitch grow when slews degrade or logic is deep and unbalanced.

Formula Or Decision Rule

• Switching: P_sw = α · C_L · V² · f
• Short-circuit: P_sc ≈ V · I_sc_avg, which rises with input transition time
• Glitch: extra transitions raise the effective α, so P_glitch = α_glitch · C_L · V² · f
• Total dynamic: P_dyn = P_sw + P_sc + P_glitch

Follow-up Question & Model Response

"How would you reduce glitch power?"

Candidate Model Response: Balance path delays into wide combinational logic so inputs arrive together, for example in adders and multiplier trees. Add a register stage to cut a very deep cone. Keep enables stable with operand isolation so data buses do not ripple through idle logic. Glitch counts only show up with timing-aware activity, so use gate-level simulation with delays to see them.