What is the difference between light-sleep, deep-sleep, and full shutdown retention states for on-chip memory, and what do they trade off?

Short Answer

Light sleep, deep sleep and shutdown are three increasingly deep memory power modes. Each one saves more leakage than the one before and takes longer to wake, and only shutdown loses the stored data. The right choice depends on how long the memory will stay idle compared with the energy and time it costs to wake it up.

Technical Explanation

• Light sleep: periphery clocks and wordlines are gated and parts of it biased down; the bit-cell array stays near full supply.
• Deep sleep: periphery powered off; the array drops to a retention voltage just above its data-retention limit, so data survives.
• Shutdown: array and periphery both off; leakage is lowest, but data is lost and must be reloaded or reinitialized.
• Wake cost grows with depth: a few cycles for light sleep, microseconds for deep sleep, reload time for shutdown.
• Each mode has a break-even idle time: below it, the wake energy costs more than the leakage saved.
• Mode pins and exact behavior come from the memory compiler datasheet, so read it rather than assuming a standard.
• Driving the mode pins from logic that is itself off leaves the memory in an undefined mode.

# Conceptual (not a tool command)
if idle_us < 2:
    stay_active()
elif idle_us < 50:
    enter_light_sleep()
elif idle_us < 20000:
    enter_deep_sleep()
else:
    save_needed_lines()
    enter_shutdown()

Follow-up Question & Model Response

"Who controls these modes, hardware or software?"

Candidate Model Response: Usually both. A hardware power controller in the always-on domain drives the memory mode pins and handles the timing between steps. Software or firmware picks the target mode based on the expected idle time. The mode pins must come from always-on logic, because the controller has to wake the memory from a state where its own domain may be off. Isolation on the memory outputs also has to be active before the array or periphery drops, or downstream logic sees X values while the memory is asleep.