What is DTCMOS (Dynamic Threshold CMOS), and how does tying the body to the gate differ from VTCMOS?
From PDVerse Low-Power Physical Design Mentor Guide, part of the pdVerse Mentor Guide
Short Answer
DTCMOS ties each transistor's body to its own gate, so the threshold voltage follows the input. When the gate turns the device on, the body forward-biases and Vt drops for more drive; when the gate is off, the body returns to the source level and Vt stays high for low leakage. There is no bias generator, but the supply must stay below the body diode turn-on voltage, which limits DTCMOS to very low-voltage designs.
Technical Explanation
- Gate-body tie: the gate signal also drives the body, so every switching event biases the body automatically.
- On: the forward-biased body lowers Vt, raising drive current. Off: body at source potential, Vt at its normal high value.
- Diode limit: the body-source junction conducts hard around 0.6 V in silicon, so VDD must stay below that.
- Each transistor needs its own isolated body, which means SOI or triple-well processes and larger cell area.
- The gate now drives the body capacitance too, so input capacitance rises and part of the speed gain is lost.
- VTCMOS versus DTCMOS: VTCMOS switches a whole block between two bias states under a mode signal; DTCMOS biases each transistor on every transition.
- Running DTCMOS above the diode limit turns the junction into a current path, raising static current instead of cutting it.
Common Mistake
The Trap: Using DTCMOS cells at a normal core voltage such as 0.9 V because they looked faster in a low-voltage datasheet.
- The body-source diode turns on, so the input drives DC current into the body on every high input.
- Static power climbs and input levels sag, which defeats the reason for using the technique. The driver also has to supply that body current, so its own output may no longer reach a clean logic high.
Follow-up Question & Model Response
"Why is DTCMOS mostly seen on SOI rather than bulk CMOS?"
Candidate Model Response: Each transistor needs a body it can drive on its own. In bulk CMOS, NMOS devices share the substrate, so tying one body to one gate would tie them all together. SOI gives each transistor an isolated body naturally, and triple-well bulk can do it at an area cost. That isolation requirement, plus the low-voltage limit, keeps DTCMOS in niche ultra-low-voltage designs. Some designs use it only on a few speed-critical transistors to limit the area cost.
Practical Example
Design Scenario: (illustrative) A sensor front end in PD_AON runs at 0.45 V on an SOI process. With DTCMOS inverters, an on-transistor sees 0.45 V of forward body bias, which lowers its Vt and roughly doubles drive current compared with a grounded body. When off, leakage matches a normal high-Vt device. Running the same cells at 0.9 V would forward-bias the body diode, so the team keeps PD_AON at 0.45 V and uses standard cells everywhere else. The input capacitance of each DTCMOS gate is about 30% higher because the driver also charges the body, so the team upsizes the drivers feeding them. Signals leaving PD_AON for the 0.9 V core pass through low-to-high level shifters, as with any other low-voltage domain.
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